mc33274d资料 | |
mc33274d |
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file size : 116 kb
manufacturer: description:no connection a logic i/o port. external encode clock input or internal data clock output. clock frequency is dependent upon clock mode 1, 2 inputs and xtal frequency (see clock mode pins). the encoder digital output. this is a three-state output whose condition is set by the data enable and powersave inputs. see table 2. when this pin is at a logical 0 the encoder is forced to an idle state and the encoder digital output is 0101, a perfect idle pattern. when this pin is a logical 1 the encoder encodes as normal. internal 1m pullup. data is made available at the encoder output pin by control of this input. see encoder output pin. internal 1 m pullup. no connection normally at vdd/2 bias, this pin should be externally decoupled by capacitor c4. internally pulled to vss when powersave is a logical 0. the analog signal input. internally biased at vdd/2, this input requires an external coupling capacitor. the source impedance should be less than 100 . output channel noise levels will improve with an even lower source impedance. see figure 2. negative supply no connection the recovered analog signal is output at this pin. it is the buffered output of a lowpass filter and requires external components. during powersave this output is open circuit. no connection a logic 0 at this pin puts most parts of the codec into a quiescent non-operational state. when at a logical 1, the codec operates normally. internal 1 m pullup. no connection a logic 0 at this pin gates a 0101... pattern internally to the decoder so that the decoder output goes to vdd/2. when this pin is a logical 1 the decoder operates as normal. internal 1m pullup. |
1pcs | 100pcs | 1k | 10k | ||
型 号:mc33274d 厂 家: 封 装:0610 批 号: 数 量:4500 说 明: |
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运 费: 所在地: 新旧程度: |
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