mmbt2907awt1资料 | |
mmbt2907awt1 |
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file size : 116 kb
manufacturer: description:as shown in figure 4, the falling edge of the 8 khz input signal (c8kb for dpll #2 or f0i for dpll # 1) is used to sample the internally generated 8 khz clock and the correction signal (cs) once in every frame (125 µs). if the sampled cs is 1, then the dpll makes a speed-up or slow-down correction depending upon the sampled value of the internal 8 khz signal. a sampled 0 or 1 causes the frequency correction circuit to respectively stretch or shrink the master clock by half a period at one instant in the frame. if the sampled cs is 0, then the dpll makes no correction on the master clock input. note that since the internal 8 khz signal and the cs signal are derived from the master clock, a correction will cause both clocks to stretch or shrink simultaneously by an amount equal to half the period of the master clock. |
1pcs | 100pcs | 1k | 10k | ||
型 号:mmbt2907awt1 厂 家: 封 装:0610 批 号: 数 量:5000 说 明: |
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运 费: 所在地: 新旧程度: |
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联系人:林浩/林妮 |
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