n80c52资料 | |
n80c52 |
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file size : 116 kb
manufacturer: description:test clock input from the backplane: this is the master clock signal that controls all scan operations of the sta111 and of the local scan ports. this input has no pull-up resistor and no esd clamp diode (esd is controlled with an alternate method). when the device is power-off (vdd floating), this input appears to be a capacitive load to ground (note 4). when vdd = 0v (i.e.; not floating but tied to vss) this input appears to be a capacitive load to ground. |
1pcs | 100pcs | 1k | 10k | ||
型 号:n80c52 厂 家: 封 装:0529 批 号: 数 量:3015 说 明: |
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