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| tps76050dbvr资料 | |
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tps76050dbvr |
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file size : 116 kb
manufacturer: description: the qs5919t clock driver uses an internal phase locked loop (pll) to lock low skew outputs to one of two reference clock inputs. eight outputs are available: 2xq, q0-q4, q5, q/2. careful layout and design ensure < 350ps skew between the q0-q4, and q/2 outputs. the qs5919t includes an internal rc filter which provides excellent jitter characteristics and eliminates the need for external components. various combinations of feedback and a divide-by-2 in the vco path allow applications to be customized for linear vco operation over a wide range of input sync frequencies. the pll can also be disabled by the pll_en signal to allow low frequency or dc testing. the lock output asserts to indicate when phase lock has been achieved. the qs5919t is designed for use in high- performance workstations, multi-board computers, networking hardware, and mainframe systems. several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribu- tion networks. |
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| 1pcs | 100pcs | 1k | 10k | ||
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型 号：tps76050dbvr 厂 家： 封 装：0529 批 号：dip/sop 数 量：3000 说 明： |
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运 费： 所在地： 新旧程度： |
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| 联系人：林浩/林妮 |
| 电 话：0755-82532799/82532766/83989559 |
| 手 机：13510168121/13725556003 |
| qq：496982847/351622092 |
| msn：linearic@hotmail.com |
| 传 真：0755-82532766 |
| email：maxim_zi@126.com |
| 公司地址： 深圳市福田区佳和大厦b座1802室 门市部：华强广场 q2a114展销柜 |
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