uc3856n资料 | |
uc3856n |
|
file size : 116 kb
manufacturer: description:found in each i/o cell. each output has individual, pro- grammable i/o tri-state control (oe), output latch clock (clk), clock enable (clken), and two multiplexer con- trol (mux0 and mux1) inputs. polarity for these signals is programmable for each i/o cell. the mux0 and mux1 inputs control a fast 4:1 mux, allowing dynamic selection of up to four signal sources for a given output. a wider 16:1 mux can be implemented with the mux expander feature of each i/o and a propagation delay increase of 2.0ns. oe, clk, clken, and mux0 and mux1 inputs can be driven directly from selected sets of i/o pins. optional dedicated clock input pins give minimum clock- to-output delays. clk and clken share the same set of i/o pins. clken disables the register clock when clken = 0. |
1pcs | 100pcs | 1k | 10k | ||
型 号:uc3856n 厂 家: 封 装:0607 批 号:dip/sop 数 量:2365 说 明: |
|||||
运 费: 所在地: 新旧程度: |
|||||
联系人:林浩/林妮 |
电 话:0755-82532799/82532766/83989559 |
手 机:13510168121/13725556003 |
qq:496982847/351622092 |
msn:linearic@hotmail.com |
传 真:0755-82532766 |
email:maxim_zi@126.com |
公司地址: 深圳市福田区佳和大厦b座1802室 门市部:华强广场 q2a114展销柜 |