ucc3172adwp资料 | |
ucc3172adwp |
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file size : 116 kb
manufacturer: description:source code: ◊ vhdl source code or/and ◊ verilog source code or/and ◊ encrypted, or plain text edif netlist vhdl & verilog test bench environment ◊ active-hdl automatic simulation macros ◊ modelsim automatic simulation macros ◊ tests with reference responses technical documentation ◊ installation notes ◊ hdl core specification ◊ datasheet synthesis scripts example application technical support ◊ ip core implementation support ◊ 3 months maintenance |
1pcs | 100pcs | 1k | 10k | ||
型 号:ucc3172adwp 厂 家: 封 装:0633 批 号:dip/sop 数 量:3362 说 明: |
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运 费: 所在地: 新旧程度: |
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联系人:林浩/林妮 |
电 话:0755-82532799/82532766/83989559 |
手 机:13510168121/13725556003 |
qq:496982847/351622092 |
msn:linearic@hotmail.com |
传 真:0755-82532766 |
email:maxim_zi@126.com |
公司地址: 深圳市福田区佳和大厦b座1802室 门市部:华强广场 q2a114展销柜 |